The present invention relates generally to generating a phase-locked output signal, and more particularly to a method and apparatus for generating a phase-locked output signal in a Fractional_N phase-locked loop.
Phase-locked loops PLLs) are widely used in many different applications. One typical application for PLLs is in variable frequency synthesizers. Variable frequency synthesizers are capable of providing stable and accurate signals with low spurious components, low phase noise, and fast switching between selected frequencies.
However, the resolution of the output frequency of a conventional PLL with an integer divide ratio is limited to N*(input frequency), where N is the integer divide ratio. To achieve a finer frequency resolution, a Fractional_N technique often is employed. The Fractional_N technique temporally alternates the divide ratio in the PLL between N and N+1. The output frequency then becomes (N+r)*(input frequency) where r is the fraction of the time that the divide ratio is N+1. Typically, the divide ratio is alternated using a frequency divider whose divide ratio is dynamically alternated between N and N+1 to produce an average divide ratio equal to a desired non-integer divide ratio. In some embodiments, it is advantageous to use a wider divide ratio range that extends from N−1 to N+2 with an average divide ratio of N+r. The principle of operation of such embodiment remains unchanged from an embodiment in which the divide ratios are N and N+1.
Although Fractional-N PLLs are capable of producing output signals with a fine frequency resolution, these PLLs have several performance disadvantages. For example, dynamically alternating the divide ratio generates quantization noise and frequency spurs in the output signal. The quantization noise and frequency spurs may degrade the performance of the instrument or system in which the Fractional-N PLL is used. Quantization noise is undesirable in most systems as it introduces errors in the output signal of the Fractional_N PLL.
To reduce quantization noise and frequency spurs, a circuit called a sigma-delta modulator is used in PLLs to generate a divide ratio sequence for controlling the divide ratio of the frequency divider. Using a suitable sigma-delta modulator moves some of the quantization noise and frequency spurs out of the frequency range of interest so that the quantization noise and frequency spurs can be filtered from the output of the phase comparator. Typically, a loop filter is used to filter the output of the phase comparator and produce an output signal of the Fractional_N PLL that is relatively free of quantization noise and frequency spurs. However, residual quantization noise and frequency spurs remain at a level too high for certain applications.
Although attempts have been made to deal with the problems associated with residual quantization noise and frequency spurs, existing solutions are complex and expensive to implement due to the complexity of the circuitry required. Solutions to these problems have long been sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.